VHDL's Crown Jewel

In this post, I would like to talk about VHDL’s crown jewel: how it preserves determinism in a concurrent language.

What you see in VHDL is the delta cycle algorithm in action. Delta cycles are an HDL concept used to order events that occur in zero physical time. A delta cycle starts with a number of signal value updates. A signal value update may trigger a number of processes. In the second phase of the delta cycle, these processes are evaluated. In these processes, signals assignments may occur that schedule value updates in the next delta cycle.

The point of the delta cycle algorithm is that signal value updates and process evaluations are kept in separate sets. The signal set is always handled completely before the process set. The order within each set is not relevant for the result. In other words, the result is deterministic even though the execution order within each set is not.

In Verilog, value update events may validly appear before or after process evaluations. Depending on execution order, the processes will see different values. Therefore, the result is non-deterministic.

In VHDL, you cannot use ordinary variables to communicate between processes. VHDL has special objects for that purpose: signals. Signals accomplish two things: the value update event is delayed to a future delta cycle, and it is held in a dedicated set that is processed atomically. In contrast, Verilog doesn’t have anything like signals. The procedural thing that holds value is called a reg. Verilog has two types of procedural assignment: blocking and nonblocking. Using blocking assignments for communication is unsafe. Nonblocking assignments are an improvement but they don't solve the problem in general because Verilog does not handle value update events and process evaluation events in separate phases.

VHDL’s delta cycle algorithm is its crown jewel. It gives you built-in determinism. While VHDL has a few exotic nondeterministic corners like shared variables, they are rarely an issue in practice. In contrast, the blocking/nonblocking issue in Verilog invariably returns to haunt designers.