Show HN: Auto-Architecture: Karpathy's Loop, Pointed at a CPU

A new experiment applied Andrej Karpathy's autonomous research loop to CPU microarchitecture design, achieving a 92% performance boost and surpassing human-optimized benchmarks in under 10 hours.
What happens when you take an autonomous research loop out of its comfort zone and aim it at a domain it has no business being good at? Andrej Karpathy's autoresearch showed that a coding agent, given two days and a single-GPU nanochat, finds 20 training-time optimizations on its own. The recipe is general — propose, implement, measure, keep the wins — but the demonstration was inside the agent's home turf: Python, gradient descent, well-known knobs.
I wanted to know if it generalized. So I pointed it at a CPU.
auto-arch-tournament is a 5-stage in-order RV32IM core in SystemVerilog — the textbook pipeline you'd write in a graduate architecture class. No caches, no branch predictor, no multi-issue on day one. Those are research-loop hypotheses, not features.
The orchestrator is hardcoded. The LLM never edits it. Each round, three slots run in parallel:
- The agent proposes a microarchitectural hypothesis as YAML, schema-checked against
schemas/hypothesis.schema.json. - An implementation agent edits files under
rtl/in an isolated git worktree. - The eval gate runs: riscv-formal (53 symbolic BMC checks), Verilator cosim (RVFI byte-identical against a Python ISS), and 3-seed nextpnr P&R on a Gowin GW2A-LV18 (Tang Nano 20K).
Improvement → merged into the trunk, becomes the new baseline. Regression / broken / placement-failed → worktree destroyed.
Baseline locked at 2.23 CoreMark/MHz, 301 iter/s. The human benchmark is VexRiscv's published 2.57 CoreMark/MHz @ 144 MHz. Then I let it run. 73 hypotheses, 9h 51m wall-clock.
| Outcome | Count | |---|---| | Improvement (accepted) | 10 | | Regression | 50 | | Broken (formal/cosim) | 9 | | Placement failed | 4 |
End state: 2.91 CoreMark/MHz, 577 iter/s, 199 MHz Fmax, 5,944 LUT4. That is +92% over the locked baseline and +56% over VexRiscv on CoreMark iter/sec, with 40% fewer LUTs.
The agent loop is a producer. The verifier is the only thing standing between you and a confidently-wrong number. The next wave of companies is not going to be people writing code. It's going to be people writing verifiers, with a loop running against them. The loop is commodity. The verifier is not. It is the artifact that encodes what your business actually means by correct.
Source: Hacker News















