PicoZ80 – Drop-In Z80 Replacement

picoZ80

Overview

The picoZ80 continues the tranZPUter theme, replacing a physical Z80 in a host or industrial computer with a faster CPU, more memory, virtual devices, networking (WiFi, BT), rapid application loading from SD card and WiFi management. RP2350B microcontroller – a dual-core 150MHz Cortex-M33 device capable of running at up to 300MHz – whose programmable I/O (PIO) state machines take full, cycle-accurate control of the Z80 address, data, and control buses. ESP32 co-processor provides WiFi and Bluetooth connectivity, SD-card mass storage, and a browser-based management interface. All configuration is driven from a single human-readable config.json file stored on the SD card, meaning no recompilation is required to reconfigure the board's memory map, ROM images, or driver selection.

• Drop-in Z80 replacement: Installs in any Z80 DIP-40 socket. The host sees normal Z80 bus timing throughout.
• Cycle-accurate PIO bus interface: Three RP2350 PIO state machines handle address, data, and control signals simultaneously at full Z80 bus speed.
• Large memory space: 8MB PSRAM organised as 64 banks x 64KB, giving a total of 4MB of banked address space accessible per CPU context.
• ROM/RAM banking: Memory blocks are configurable in 512-byte granularity and can be mapped as ROM, RAM, physical host memory, or virtual function handlers.
• Virtual device framework: Any 512-byte block of memory or I/O port range can be backed by a C function, enabling fully virtualised peripherals.
• Machine personas: The Z80 firmware can be configured via a JSON config to work within any Z80 host. Personas are being developed to add virtual drivers to the host, using the resources of the RP2350/ESP32. Already the MZ-700 persona has a rich repertoire of drivers and this will be extended to the MZ-80A, MZ-80B, MZ-800 and other Sharp machines.
• Floppy and QuickDisk emulation: WD1773-compatible floppy disk controller and Sharp QuickDisk drive emulation, using DSK/RAW images on the SD card.
• WiFi and web management: The onboard ESP32 provides a seven-page Bootstrap web interface for configuration, file management, OTA firmware updates, and persona selection.
• Dual firmware partitions: Two independent 5MB firmware slots allow safe OTA upgrades; the active partition is selected from the web interface or bootloader.
• USB firmware update: The bootloader exposes a USB bridge for firmware flashing without requiring a hardware debugger.

Hardware

The picoZ80 PCB (revision 2.5) is a compact, multi-layer board designed to fit within the physical footprint of the Z80 DIP-40 package. All logic operates at 3.3V; level shifting and drive current considerations for the 5V host bus are handled in the schematic design.

Key Components

• RP2350B (Cortex-M33 dual-core): Primary processor, running at up to 300MHz. Executes the Z80 emulation hot loop on Core 1 and handles file I/O, USB, and ESP32 relay on Core 0.
• 16MB SPI Flash: Stores the bootloader, application firmware slots, and configuration partitions.
• 8MB PSRAM (SPI): External pseudo-static RAM providing banked address space for the emulated CPU.
• ESP32 co-processor: Provides WiFi, Bluetooth, SD-card reader, and web server. Communicates with the RP2350 via a binary IPC protocol over 50MHz FSPI.
• 3.3V power supply: Efficient buck converter drawing from the 5V present on the Z80 socket VCC pin.

Architecture

Dual-Core Design

The RP2350B's two Cortex-M33 cores are given completely separate responsibilities:

• Core 0 handles all non-real-time tasks: USB bridge, firmware update coordination, file I/O (relayed to the ESP32), ESP32 command dispatch, and watchdog supervision.
• Core 1 runs the CPU emulation hot loop exclusively. It services the PIO FIFOs to process Z80 bus transactions, resolves each address against the memory map, and services it from PSRAM or virtual device handlers.

PIO Bus Interface

The Z80 bus interface is implemented entirely in RP2350 PIO assembly (z80.pio). The firmware uses all three PIO blocks to handle the 16-bit address bus, bidirectional 8-bit data bus, and all control signals (MREQ, IORQ, RD, WR, etc.) in synchrony.