OpenBSD on Motorola 88000 Processors

(Follow this link to go back to the main m88k page.)

Many people know, or have heard of, the Motorola 68000 architecture. These processors have been used in many machines: in the first generations of Apple Macintosh computers, in the ever-rivals Amiga and Atari ST home computers, in many workstations built by Sun, HP and NeXT (to name only a few), but also in many industrial systems and boards built by Motorola, Tadpole, Heurikon or Performance Technologies (to name only a few.)

The 68000 architecture has been very successful, but due to its CISC nature with complex addressing modes and many instructions, Motorola was not able to keep up in the speed competition.

In order to be able to deliver performance and megahertz, another processor architecture was needed, one which could scale more easily.

At this point you're probably expecting me to write about the PowerPC, which also turned out to be a successful architecture, used in the next generations of Apple Macintosh computers, in workstations (from IBM and Bull, mostly), and in the iconic BeBox.

But between the 68000 and the PowerPC, there's the black sheep of the family. A processor architecture which made a lot of promises, but did not deliver them, and was destined to be consigned to oblivion, as if it had been a bad dream.

That processor architecture is the Motorola 88000 architecture, or m88k for short.

There have been two generations of 88000 processors before Motorola reassigned all its engineers to the PowerPC.

The first generation consists of the 88100 CPU, with optional external 88200 so-called CMMU: a chip which provides both cache memory and memory management facilities. The choice of separate chips allowed designs which did not need an MMU to be completed quickly and cheaply, and NCD used the 88100 a lot in its X terminals line for that reason.

All the CMMUs sit on the same so-called P-Bus with the processor, and work closely with it to perform their duties. And by the virtue of sharing that bus, they can monitor each other to achieve automatic cache coherency across processors. Moreover, they can also make themselves visible to all processors, as they answer to specific commands on dedicated address ranges: this allows a given processor to perform a cache invalidation or any MMU operation on behalf of another processor (by sending commands to the CMMUs associated to that processor) without needing to interrupt that processor. This makes multiprocessor implementation, from a software point of view, much easier than on more classical architectures.

Another perceived advantage of these separate components, is that depending upon your needs for cache memory, it is possible to use more than one 88200 chip per processor. In fact, while the basic designs would use two (one for instruction cache, one for data cache), higher performance designs could use up to eight such CMMU companions (having more than eight, in addition to becoming a serious board space problem, would also cause bus latency and signal strength problems, as all the chips had to be connected to the same high-speed P-Bus.) This limited the speed at which the 88100 and 88200 chips could run; and they were built in speeds ranging from 16MHz to 33MHz, most of them being 25MHz parts.

The second generation tries to learn from the 88100 drawbacks and reverts to a more traditional architecture, bringing back the cache and MMU into the 88110 processor (and, for systems programmers, a much simpler exception model.) Initially supposed to run at 50MHz, with the aim of reaching 100MHz in the future, these processors suffered from hardware problems, and for a while, none of the early 50MHz processors would run reliably at that speed, and had to be sold as 40MHz parts, a speed at which they did not misbehave that much...

Even though these defects were eventually fixed, and parts running faster than 50MHz even started to get produced (there is evidence of existing 60MHz chips), Motorola was more than happy to pull the plug when IBM knocked on its door asking for help with the PowerPC project, leading to the short-lived AIM (Apple, IBM, Motorola) alliance.

Some parts of the 88110 design made their way to the first PowerPC processors, in particular the external busses of the PowerPC 601 are very similar to those of the 88110.

Because of its short lifespan (roughly, 1988-1994) and, for the first generation, system design complexity, the 88000 architecture did not convince many hardware companies to build their systems on this architecture.

To this day, there isn't much information left about these systems. Paul Weissmann of OpenPA fame, had started a similar, but less ambitious, effort to document the m88k ecosystem, as "badabada". This site is no longer online, but there is a mirror of the last version of that site on the Internet Archive, as well as on the current incarnation of the m88k.com website.

The most well-known users of these processors were:

A VME system consists of a passive backplane, into which the necessary VME boards are plugged; the backplane allows several signals to be passed between all slots.

VME boards can be of any type; there exist processor boards, memory boards, I/O boards (such as Ethernet or SCSI controllers), graphics boards, signal acquisition boards...

One of the VME boards (usually the board occupying the leftmost slot) is the system controller, and is allowed to perform a few global actions, such as sending a reset signal across the whole bus.

Boards can then perform memory access cycles across the bus; bus accesses can be 8, 16 or 32-bit wide, using 16, 24 or 32-bit addresses, and also carry address modifiers (the equivalent of the 68000 function codes) which can be used to restrict accesses; these are usually used to implement cheap supervisor/user distinction, on systems which do not need full-fledged MMUs.

Boards can also send interrupt requests to the bus, with an 8-bit interrupt vector number; the interrupts are usually handled by an interrupt controller onboard the system controller.

Originally a 32-bit address and data bus, with each VME board having a 6U form factor with two large connectors plugging into the backplane, it was also possible for a board to use only one connector, reducing its bus width to 24 address bits and 16 data bits, and fit in 3U. And for larger component integration needs, a 9U form factor also existed, and was used for example by Sun for its Sun-3 and Sun-4 workstation lines (as well as some Sun-2 models), or by Encore with the 88100-based Encore 91 computers.

Near the end of the 1990s, many users of the VME bus started moving to the faster, and functionally equivalent compactPCI bus.

Quoting the manual pages from Motorola's operating system for this board:

The mvme181 is a CPU platform with an MC88100 MPU, two MC88200 CMMUs, two RS-232C serial communications ports driven by a 68692 DUART, a battery backup real-time clock/calendar, 8 MB of dual-ported onboard DRAM, and 512 KB of firmware containing the MVME181BUG Debugger and Diagnos- tic Package.

Quoting the manual pages from Motorola's operating system for this board:

The mvme187 is a CPU platform with an MC88100 MPU, two MC88200 CMMUs, 32, 40, 48, or 64 MB of dual-ported onboard (mezzanine) memory, 8 KB of battery backup static RAM, 128 Kb of volatile static RAM, a time-of-day clock/calendar, an Ethernet transceiver interface (Intel 82596CA), four EIA- 232-D serial communication ports (Cirrus Logic CD2400/2401), a SCSI-2 bus interface (NCR 53C710), a Centronics-compatible parallel printer port (except on M8120 systems), configur- able local and VMEbus address maps, four tick timers, and four ROM sockets of which two contain the MVME187BUG Debugger and Diagnostic Package. In addition, M8120 systems contain an additional Cirrus Logic CD2400 chip from which two additional serial communication ports are exposed.