Book: RISC-V System-on-Chip Design

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RISC-V System-on-Chip Design

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RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

• Covers detailed design for all components of a nontrivial microprocessor

• Provides detailed explanations on the implementation of RISC-V microprocessors

• Uses open-source SystemVerilog code and test cases for the entire processor, including single-issue and superscalar cores, multicore, all extensions (including multiplication/division, floating point, and atomic memory operations), and common peripherals

• Enables users to build scripts to implement the processor on the open-source Skywater process

• ISBN-100323994989

• ISBN-13978-0323994989

• Edition1st

• PublisherMorgan Kaufmann

• Publication dateJuly 15, 2026

• LanguageEnglish

• Dimensions7.51 x 1.21 x 9.21 inches

• Print length856 pages

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Editorial Reviews

Review

Helps readers learn how to design microprocessors and systems-on-chip using the open source RISC-V instruction set architecture

From the Back Cover

About the Author

James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library.

Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.

Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.

Product details

• Publisher : Morgan Kaufmann
• Publication date : July 15, 2026
• Edition : 1st
• Language : English
• Print length : 856 pages
• ISBN-10 : 0323994989
• ISBN-13 : 978-0323994989
• Item Weight : 15.9 ounces
• Dimensions : 7.51 x 1.21 x 9.21 inches
• Best Sellers Rank: #106,724 in Books (See Top 100 in Books)
• #6 in Integrated Circuits
• #9 in Circuit Design
• #12 in Computer Hardware Design & Architecture

About the authors

James Stine is the Edward Joullian Professor in Engineering in the School of Electrical and Computer Engineering at Oklahoma State University. He received his Ph.D. in electrical engineering from Lehigh University. He was previously with the Illinois Institute of Technology in Chicago, IL. He specializes in research and teaching in VLSI, digital arithmetic, computer system architecture, and digital design. He is also a leading developer of commercial and academic system on chip design flows for Google, Cadence Design Systems, Synopsys, Mentor Graphics and several public-domain tools. James’s interests including spending time with his family.

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