Aegis – open-source FPGA silicon

Aegis is a fully open-source FPGA, from the silicon up. Existing open-source FPGA efforts either reverse-engineer proprietary architectures or build tooling around closed silicon. Aegis starts at the other end: the fabric design is open, the toolchain is open, and the path to real silicon goes through open PDKs and shuttle services like wafer.space. The project generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape out the fabric itself to a foundry. The first Aegis device, Terra-1, targets GF180MCU. It features ~2880 LUT4s, 128 BRAM tiles, and 64 DSP tiles. The workflow is powered by Nix, supporting synthesis via Yosys and place-and-route via nextpnr. The architecture follows Xilinx-style conventions, generated by the ROHD framework in SystemVerilog.